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Author
5
Arapoyanni, A.
4
Nikolos, D.
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Efstathiou, C.
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Matakias, S.
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Kamoulakos, G.
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Limniotis, K.
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Moisiadis, Y.
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Nicolaidis, M.
1
Schoellkopf, J. P.
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Vergos, H. T.
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circuits
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design
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design for testability
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charge recycling
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cmos logic
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comparator
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concurrent testing
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current mode checker
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current monitoring
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device simulation
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journalArticle
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ΑΠΟΘΕΤΗΡΙΟ "ΟΛΥΜΠΙΑΣ"
Σχολή Θετικών Επιστημών
Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής
Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά)
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Device simulation of a n-DMOS cell with trench isolation (Journal article)
A design technique for energy reduction in NORA CMOS logic (Journal article)
Path delay fault testing of multiplexer-based shifters (Journal article)
Testable designs of multiple precharged Domino circuits (Journal article)
A current mode, parallel, two-rail code checker (Journal article)
A new technique for I(DDQ) testing in nanometer technologies (Journal article)
Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers (Journal article)
A circuit for concurrent detection of soft and timing errors in digital CMOS ICs (Journal article)