Please use this identifier to cite or link to this item:
https://olympias.lib.uoi.gr/jspui/handle/123456789/10909| Title: | A design technique for energy reduction in NORA CMOS logic |
| Institution and School/Department of submitter: | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής |
| Keywords: | charge recycling,low-power design,no race (nora) cmos circuits,recycling differential logic,power |
| URI: | https://olympias.lib.uoi.gr/jspui/handle/123456789/10909 |
| ISSN: | 1057-7122 |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| tsiatouhas-2006-A design technique for energy reduction in NORA CMOS logic.pdf | 785.85 kB | Adobe PDF | View/Open Request a copy |
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