Please use this identifier to cite or link to this item:
https://olympias.lib.uoi.gr/jspui/handle/123456789/10847| Title: | Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect |
| Institution and School/Department of submitter: | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής |
| Keywords: | asynchronous circuits,atpg,globally-asynchronous,locally-synchronous (gals),scan-testing,stuck-at fault testing,circuits,codes |
| URI: | https://olympias.lib.uoi.gr/jspui/handle/123456789/10847 |
| ISSN: | 1063-8210 |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Efthymiou-2005-Test pattern generat.pdf | 504.21 kB | Adobe PDF | View/Open Request a copy |
This item is licensed under a Creative Commons License
