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https://olympias.lib.uoi.gr/jspui/handle/123456789/10847Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Efthymiou, A. | en |
| dc.contributor.author | Bainbridge, J. | en |
| dc.contributor.author | Edwards, D. | en |
| dc.date.accessioned | 2015-11-24T17:00:58Z | - |
| dc.date.available | 2015-11-24T17:00:58Z | - |
| dc.identifier.issn | 1063-8210 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10847 | - |
| dc.rights | Default Licence | - |
| dc.subject | asynchronous circuits | en |
| dc.subject | atpg | en |
| dc.subject | globally-asynchronous | en |
| dc.subject | locally-synchronous (gals) | en |
| dc.subject | scan-testing | en |
| dc.subject | stuck-at fault testing | en |
| dc.subject | circuits | en |
| dc.subject | codes | en |
| dc.title | Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect | en |
| heal.type | journalArticle | - |
| heal.type.en | Journal article | en |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.identifier.primary | Doi 10.1109/Tvlsi.2005.862722 | - |
| heal.language | en | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.publicationDate | 2005 | - |
| heal.abstract | Asynchronous design offers a solution to the interconnect problems faced by system-on-chip (SoC) designers, but their adoption has been held back by a lack of methodology and support for post-fabrication testing. This paper first addresses the problem of testing C-elements, an important building block of asynchronous circuits. A simple method for generating test patterns is described which is shown to be applicable for a wide range of implementations. Based on the C-element testability, a partial scan technique was developed that achieves a test coverage of over 99.5% when applied to an asynchronous, network-on-chip, interconnect fabric. Test patterns are automatically generated by a custom program, given the interconnect topology. Area savings of at least 60% are noted, in comparison to standard, asynchronous, full-scan level-sensitive scan devices (LSSD) methods. | en |
| heal.journalName | Ieee Transactions on Very Large Scale Integration (Vlsi) Systems | en |
| heal.journalType | peer reviewed | - |
| heal.fullTextAvailability | TRUE | - |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Efthymiou-2005-Test pattern generat.pdf | 504.21 kB | Adobe PDF | View/Open Request a copy |
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