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https://olympias.lib.uoi.gr/jspui/handle/123456789/26732Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Panagopoulos, Ioannis | en |
| dc.contributor.author | Pavlatos, Christos | en |
| dc.contributor.author | Manis, George | en |
| dc.contributor.author | Papakonstantinou, George | en |
| dc.date.accessioned | 2015-12-12T09:51:50Z | - |
| dc.date.available | 2015-12-12T09:51:50Z | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/26732 | - |
| dc.rights | Default License | - |
| dc.subject | Computer science | en |
| dc.title | A flexible general - purpose parallelizing architecture for nested loops in reconfigurable platforms | en |
| heal.type | bookChapter | - |
| heal.type.en | Book chapter | en |
| heal.type.el | Κεφάλαιο βιβλίου | el |
| heal.generalDescription | 20 - 30 σ. | en |
| heal.language | en | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Η/Υ & Πληροφορικής | el |
| heal.publicationDate | 2007 | - |
| heal.bibliographicCitation | Βιβλιογραφία: σ. 30 | en |
| heal.publisher | Springer Berlin / Heidelberg | en |
| heal.fullTextAvailability | true | - |
| heal.bookName | Integrated circuit and system design. Power and timing modeling, optimization and simulation | en |
| Appears in Collections: | Μονογραφίες ( Κλειστές) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| A flexible general - purpose parallelizing architecture for nested loops in reconfigurable platforms.pdf | 321.42 kB | Adobe PDF | View/Open Request a copy |
This item is licensed under a Creative Commons License
