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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Manthos, N. | en |
| dc.contributor.author | Sidiropoulos, G. | en |
| dc.contributor.author | Vichoudis, P. | en |
| dc.date.accessioned | 2015-11-24T18:33:03Z | - |
| dc.date.available | 2015-11-24T18:33:03Z | - |
| dc.identifier.issn | 0018-9499 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/16680 | - |
| dc.rights | Default Licence | - |
| dc.title | An efficient hardware design for rejecting common mode in a group of adjacent channels of silicon microstrip sensors used in high energy physics experiments | en |
| heal.type | journalArticle | - |
| heal.type.en | Journal article | en |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.identifier.secondary | <Go to ISI>://WOS:000238581900068 | - |
| heal.identifier.secondary | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=1644987 | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Επιστημών και Τεχνολογιών. Τμήμα Βιολογικών Εφαρμογών και Τεχνολογιών | el |
| heal.publicationDate | 2006 | - |
| heal.abstract | Algorithms have been studied using Monte Carlo techniques and implemented in a fast Xilinx Virtex II pro field programmable gate array (FPGA), in order to calculate and remove, after pedestal subtraction, the common mode of a group of adjacent channels. The implementation of the algorithms has been optimized both for speed and minimal FPGA resources, so as to be used in multi-channel applications. The aim of this work is to define the optimum algorithm for common mode calculation to be implemented for common mode rejection in the CMS Preshower detector. | en |
| heal.journalName | Ieee Transactions on Nuclear Science | en |
| heal.journalType | peer reviewed | - |
| heal.fullTextAvailability | TRUE | - |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) - ΦΥΣ | |
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