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DC Field | Value | Language |
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dc.contributor.author | Barney, D. | en |
dc.contributor.author | Bialas, W. | en |
dc.contributor.author | Kokkas, P. | en |
dc.contributor.author | Manthos, N. | en |
dc.contributor.author | Reynaud, S. | en |
dc.contributor.author | Sidiropoulos, G. | en |
dc.contributor.author | Vichoudis, P. | en |
dc.date.accessioned | 2015-11-24T18:27:10Z | - |
dc.date.available | 2015-11-24T18:27:10Z | - |
dc.identifier.issn | 1748-0221 | - |
dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/15996 | - |
dc.rights | Default Licence | - |
dc.subject | optical detector readout concepts | en |
dc.subject | data reduction methods | en |
dc.title | Implementation of on-line data reduction algorithms in the CMS endcap preshower data concentrator cards | en |
heal.type | journalArticle | - |
heal.type.en | Journal article | en |
heal.type.el | Άρθρο Περιοδικού | el |
heal.identifier.primary | Doi 10.1088/1748-0221/2/03/P03001 | - |
heal.identifier.secondary | <Go to ISI>://000253651300001 | - |
heal.identifier.secondary | http://iopscience.iop.org/1748-0221/2/03/P03001/pdf/1748-0221_2_03_P03001.pdf | - |
heal.language | en | - |
heal.access | campus | - |
heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Επιστημών και Τεχνολογιών. Τμήμα Βιολογικών Εφαρμογών και Τεχνολογιών | el |
heal.publicationDate | 2007 | - |
heal.abstract | The CMS Endcap Preshower (ES) sub-detector comprises 4288 silicon sensors, each containing 32 strips. The data are transferred from the detector to the counting room via 1208 optical fibres running at 800Mbps. Each fibre carries data from two, three or four sensors. For the readout of the Preshower, a VME-based system, the Endcap Preshower Data Concentrator Card (ES-DCC), is currently under development. The main objective of each readout board is to acquire on-detector data from up to 36 optical links, perform on-line data reduction via zero suppression and pass the concentrated data to the CMS event builder. This document presents the conceptual design of the Reduction Algorithms as well as their implementation in the ES-DCC FPGAs. These algorithms, as implemented in the ES-DCC, result in a data-reduction factor of similar to 20. | en |
heal.journalName | Journal of Instrumentation | en |
heal.journalType | peer reviewed | - |
heal.fullTextAvailability | TRUE | - |
Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) |
Files in This Item:
File | Description | Size | Format | |
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Barney-2007-Implementation of on.pdf | 3.53 MB | Adobe PDF | View/Open Request a copy |
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