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Please use this identifier to cite or link to this item: https://olympias.lib.uoi.gr/jspui/handle/123456789/11085
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dc.contributor.authorKavousianos, X.en
dc.contributor.authorChakrabarty, K.en
dc.contributor.authorJain, A.en
dc.contributor.authorParekhji, R.en
dc.date.accessioned2015-11-24T17:02:42Z-
dc.date.available2015-11-24T17:02:42Z-
dc.identifier.issn0278-0070-
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/11085-
dc.rightsDefault Licence-
dc.subjectinteger programmingen
dc.subjectlinear programmingen
dc.subjectlow-power electronicsen
dc.subjectmultiprocessing systemsen
dc.subjectschedulingen
dc.subjectsystem-on-chipen
dc.subjectcore switchesen
dc.subjectdefect screeningen
dc.subjectdynamic voltage scalingen
dc.subjectfast heuristic methodsen
dc.subjectinteger linear programmingen
dc.subjectlow power consumptionen
dc.subjectmulticore system-on-chipen
dc.subjectmultivoltage domain testingen
dc.subjectpower supply voltage levelsen
dc.subjectstate retentionen
dc.subjecttest costen
dc.subjecttest schedule optimizationen
dc.subjecttest timeen
dc.subjectvoltage islandsen
dc.subjectComplexity theoryen
dc.subjectJob shop schedulingen
dc.subjectMulticore processingen
dc.subjectOptimizationen
dc.subjectSchedulesen
dc.subjectSystem-on-a-chipen
dc.subjectTestingen
dc.subjectCore-based testingen
dc.subjectSoC test schedulingen
dc.subjectmulticore systems-on-a-chip (SoCs)en
dc.titleTest Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islandsen
heal.typejournalArticle-
heal.type.enJournal articleen
heal.type.elΆρθρο Περιοδικούel
heal.identifier.primary10.1109/tcad.2012.2203600-
heal.accesscampus-
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικήςel
heal.publicationDate2012-
heal.abstractIn order to provide high performance with low power consumption, many multicore chips employ dynamic voltage scaling and voltage islands that operate at multiple power-supply voltage levels. Effective defect screening for such chips requires test applications at different operating voltages, which leads to higher test time and test cost compared to systems-on-a-chip (SoCs), which operate at only a single voltage level. We propose test scheduling techniques to minimize the testing time for multicore chips when each core is tested at multiple voltage levels and when it is tested for state retention when the core switches between two voltage levels. The proposed techniques include exact optimization based on integer linear programming and fast heuristic methods. Experimental results for two test-case SoCs from the industry highlight the effectiveness of the proposed method.en
heal.journalNameComputer-Aided Design of Integrated Circuits and Systems, IEEE Transactions onen
heal.journalTypepeer reviewed-
heal.fullTextAvailabilityTRUE-
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