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dc.contributor.authorKavousianos, X.en
dc.contributor.authorBakalis, D.en
dc.contributor.authorNikolos, D.en
dc.date.accessioned2015-11-24T17:02:05Z-
dc.date.available2015-11-24T17:02:05Z-
dc.identifier.issn1084-4309-
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/11010-
dc.rightsDefault Licence-
dc.subjectalgorithmsen
dc.subjectdesignen
dc.subjectreliabilityen
dc.subjectlow-power testingen
dc.subjectscan-based testingen
dc.subjectscan cell gatingen
dc.subjectpartial gatingen
dc.subjectcircuitsen
dc.subjectcoresen
dc.titleEfficient Partial Scan Cell Gating for Low-Power Scan-Based Testingen
heal.typejournalArticle-
heal.type.enJournal articleen
heal.type.elΆρθρο Περιοδικούel
heal.identifier.primaryDoi 10.1145/1497561.1497571-
heal.languageen-
heal.accesscampus-
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικήςel
heal.publicationDate2009-
heal.abstractGating of the outputs of a portion of the scan cells (partial gating) has been recently proposed as a method for reducing the dynamic power dissipation during scan-based testing. We present a new systematic method for selecting, under area and performance design constraints, the most suitable for gating subset of scan cells as well as the proper gating value for each one of them, aiming at the reduction of the average switching activity during testing. We show that the proposed method outperforms the corresponding already known methods, with respect to average dynamic power dissipation reduction.en
heal.journalNameAcm Transactions on Design Automation of Electronic Systemsen
heal.journalTypepeer reviewed-
heal.fullTextAvailabilityTRUE-
Appears in Collections:Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά)

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