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https://olympias.lib.uoi.gr/jspui/handle/123456789/10960Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Tsiatouhas, Y. E. | en |
| dc.date.accessioned | 2015-11-24T17:01:40Z | - |
| dc.date.available | 2015-11-24T17:01:40Z | - |
| dc.identifier.issn | 1549-7747 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10960 | - |
| dc.rights | Default Licence | - |
| dc.subject | embedded negative voltage-level converter | en |
| dc.subject | level shifter | en |
| dc.subject | level conversion | en |
| dc.subject | mos-device voltage stress relaxation | en |
| dc.subject | charge-pump circuits | en |
| dc.subject | flash memories | en |
| dc.subject | word-line | en |
| dc.subject | design | en |
| dc.subject | scheme | en |
| dc.subject | drams | en |
| dc.subject | cell | en |
| dc.subject | generator | en |
| dc.subject | eeprom | en |
| dc.subject | gate | en |
| dc.title | A stress-relaxed negative voltage-level converter | en |
| heal.type | journalArticle | - |
| heal.type.en | Journal article | en |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.identifier.primary | Doi 10.1109/Tcsii.2006.886877 | - |
| heal.language | en | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.publicationDate | 2007 | - |
| heal.abstract | In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mu m triple-well standard CMOS technology, using double-gate-oxidethickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported. | en |
| heal.journalName | Ieee Transactions on Circuits and Systems Ii-Express Briefs | en |
| heal.journalType | peer reviewed | - |
| heal.fullTextAvailability | TRUE | - |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| tsiatouhas-2007-A stress-relaxed negative voltage-level converter.pdf | 601 kB | Adobe PDF | View/Open Request a copy |
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