Please use this identifier to cite or link to this item:
https://olympias.lib.uoi.gr/jspui/handle/123456789/10937Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Kavousianos, X. | en |
| dc.contributor.author | Kalligeros, E. | en |
| dc.contributor.author | Nikolos, D. | en |
| dc.date.accessioned | 2015-11-24T17:01:30Z | - |
| dc.date.available | 2015-11-24T17:01:30Z | - |
| dc.identifier.issn | 0278-0070 | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10937 | - |
| dc.rights | Default Licence | - |
| dc.subject | embedded testing techniques | en |
| dc.subject | huffman encoding | en |
| dc.subject | intellectual property (ip) cores | en |
| dc.subject | linear feedback shift registers (lfsrs) | en |
| dc.subject | test-data compression | en |
| dc.subject | embedded deterministic test | en |
| dc.subject | twisted-ring counters | en |
| dc.subject | built-in-test | en |
| dc.subject | a-chip test | en |
| dc.subject | pattern generation | en |
| dc.subject | scan chains | en |
| dc.subject | data volume | en |
| dc.subject | test time | en |
| dc.subject | reduction | en |
| dc.subject | circuits | en |
| dc.title | Multilevel Huffman coding: An efficient test-data compression method for IP cores | en |
| heal.type | journalArticle | - |
| heal.type.en | Journal article | en |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.identifier.primary | Doi 10.1109/Tcad.2006.885830 | - |
| heal.language | en | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.publicationDate | 2007 | - |
| heal.abstract | A new test-data compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman codeword corresponds to three different kinds of information, and thus, significant compression improvements compared to the already known techniques are achieved. A simple architecture is proposed for decoding the compressed data on chip. Its hardware overhead is very low and comparable to that of the most efficient methods in the literature. Moreover, the major part of the decompressor can be shared among different cores, which reduces the hardware overhead of the proposed architecture considerably. Additionally, the proposed technique offers increased probability of detection of unmodeled faults since the majority of the unknown values of the test sets are replaced by pseudorandom data generated by a linear feedback shift register. | en |
| heal.journalName | Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems | en |
| heal.journalType | peer reviewed | - |
| heal.fullTextAvailability | TRUE | - |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Kavousianos-2007-Multilevel Huffman c.pdf | 539.02 kB | Adobe PDF | View/Open Request a copy |
This item is licensed under a Creative Commons License
