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dc.contributor.authorEfthymiou, A.en
dc.contributor.authorGarside, J. D.en
dc.date.accessioned2015-11-24T17:00:38Z-
dc.date.available2015-11-24T17:00:38Z-
dc.identifier.issn1063-8210-
dc.identifier.urihttps://olympias.lib.uoi.gr/jspui/handle/123456789/10794-
dc.rightsDefault Licence-
dc.subjectasynchronous designen
dc.subjectcontent-addressable memoryen
dc.subjectlow-power designen
dc.titleA CAM with mixed serial-parallel comparison for use in low energy cachesen
heal.typejournalArticle-
heal.type.enJournal articleen
heal.type.elΆρθρο Περιοδικούel
heal.identifier.primaryDoi 10.1109/Tvlsi.2004.824298-
heal.languageen-
heal.accesscampus-
heal.recordProviderΠανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικήςel
heal.publicationDate2004-
heal.abstractA novel, low-energy content addressable memory (CAM) structure is presented which achieves an approximately four-fold improvement in energy per access, compared to a standard parallel CAM, when used as tag storage for caches. It exploits the address patterns commonly found in application programs, where testing the four least significant bits of the tag is sufficient to determine over 90% of the tag mismatches; the proposed CAM checks those bits first and evaluates the remainder of the tag only if they match. Although, the energy savings come at the cost of a 25% increase in search time, the proposed CAM organization also supports a parallel operating mode without a speed loss but with reduced energy savings.en
heal.journalNameIeee Transactions on Very Large Scale Integration (Vlsi) Systemsen
heal.journalTypepeer reviewed-
heal.fullTextAvailabilityTRUE-
Appears in Collections:Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά)

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