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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Bakalis, D. | en |
| dc.contributor.author | Kavousianos, X. | en |
| dc.contributor.author | Vergos, H. T. | en |
| dc.contributor.author | Nikolos, D. | en |
| dc.contributor.author | Alexiou, G. P. | en |
| dc.date.accessioned | 2015-11-24T17:00:03Z | - |
| dc.date.available | 2015-11-24T17:00:03Z | - |
| dc.identifier.issn | 1065-514X | - |
| dc.identifier.uri | https://olympias.lib.uoi.gr/jspui/handle/123456789/10699 | - |
| dc.rights | Default Licence | - |
| dc.subject | array multipliers | en |
| dc.subject | modified-booth multipliers | en |
| dc.subject | built-in self-test | en |
| dc.subject | low power testing | en |
| dc.subject | vlsi testing | en |
| dc.subject | heat dissipation | en |
| dc.subject | bist | en |
| dc.title | Low power built-in self-test schemes for array and booth multipliers | en |
| heal.type | journalArticle | - |
| heal.type.en | Journal article | en |
| heal.type.el | Άρθρο Περιοδικού | el |
| heal.language | en | - |
| heal.access | campus | - |
| heal.recordProvider | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής | el |
| heal.publicationDate | 2001 | - |
| heal.abstract | Recent trends in IC technology have given rise to a new requirement, that of low power dissipation during testing, that Built-In Self-Test (BIST) structures must target along with the traditional requirements. To this end, by exploiting the inherent properties of Carry Save, Carry Propagate and modified Booth multipliers, in this paper we propose new power-efficient BIST structures for them. The proposed BIST schemes are derived by: (a) properly assigning the Test Pattern Generator (TPG) outputs to the multiplier inputs, (b) modifying the TPG circuits and (c) reducing the test set length. Our results indicate that the total power dissipated during testing can be reduced from 29.3% to 54.9%, while the average power per test vector applied can be reduced from 5.8% to 36.5% and the peak power dissipation can be reduced from 15.5% to 50.2% depending on the implementation of the basic cells and the size of the multiplier. The test application time is also significantly reduced, while the introduced BIST schemes implementation area is small. | en |
| heal.journalName | Vlsi Design | en |
| heal.journalType | peer reviewed | - |
| heal.fullTextAvailability | TRUE | - |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| Bakalis-2001-Low power built-in s.pdf | 2.78 MB | Adobe PDF | View/Open |
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