System-on-chip testing (Doctoral thesis)
We already live in the era of Internet of Things. The common devices we use daily are connected together and are getting "smarter" rapidly. In every device belonging in IoT, there is an SoC. In order to satisfy the continuous increased requirements of the new era, SoCs are constantly evolving. 3D-ICs is a promising solution to satisfy the demands of the new era and seem to secure the continuation of Moore's Law for the near future. 3D-ICs achieve higher packing density and higher performance than 2D-ICs and reduce the cost of wiring and power consumption. Recently, the semiconductor companies released products based on 3D-ICs. This research focuses in the development of new TAM architectures and test-scheduling methods for 3D-SoCs, which exploit the high speed offered by TSVs, while power and thermal constraints are met. We introduce a new TAM architecture for 3D SoCs, which minimizes the test-time, the number of TSVs, and TAM lines used for transferring test-data to the cores. The test schedule is calculated by a very effective TDM method, and a highly efficient optimization method based on rectangle-packing and simulated-annealing. Experiments have shown that as much as 9.6x better test time can be achieved using the proposed method, especially under strict power and thermal constraints. The previous method is compatible only with bus-based TAMs, which require long interconnection wires and many buffers at each die of the stack, therefore they fail to fully exploit the high frequencies of the global channels. In order to overcome the limitations of the previous method, we propose a new TDM-based 3D TAM architecture, which uses daisy-chains and offers higher test-time benefits and significantly lower interconnection overhead. This research also focuses in the improvement of the defect screening of processor-based devices. The continually increasing demands of the market for higher computational performance at lower cost and power consumption drive processor vendors to develop new microprocessor generations, which introduce new challenges on processor-based device testing. The need to test the processor-based devices at the normal mode of operation, impose the complementary use of non-intrusive test methods, such as SBST. Most SBST techniques often target only the stuck-at fault model, which is inadequate for detecting many defects. SBST methods also require extensive human intervention and long development times. Moreover, they involve the CPU-intensive process of fault-simulating multi-million gate designs for multi-million clock cycles using multiple fault models and specialized functional (non-scan) simulators. We introduce the first fault-independent SBST method, which offers short test-program generation time under strict test-application-time and test-program-size constraints. The test-programs are evaluated by means of a novel and very effective SBST-oriented probabilistic metric, which considers both the architectural model and the synthesized gate-level netlist of the DUT. The proposed metric, which is based on output deviations, can be calculated very quickly as it omits the time-consuming functional fault-simulation, and it can be applied to any SBST-based method.
|Institution and School/Department of submitter:||Πανεπιστήμιο Ιωαννίνων. Πολυτεχνική Σχολή. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής|
|Keywords:||Testing,3d-soc,Tsv,Tdm,SBST,Daisy-chains,Έλεγχος,3-διάστατα ολοκληρωμένα κυκλώματα,Διασυνδέσεις-μέσω-πυριτίου,Χρονική πολυπλεξία,Αυτο-έλεγχος λογισμικού,Σειριακές αλυσίδες|
|Appears in Collections:||Διδακτορικές Διατριβές|
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|Δ.Δ. GEORGIOU PANAGIOTIS 2019.pdf||12.96 MB||Adobe PDF||View/Open|
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