Advanced methods for testing multi-core SoCs (Doctoral thesis)
We are in the dawn of a new era of “Internet of Things”. Novel home and business “things” appear rapidly, and they promise to improve the quality of our lives and grow the world's economy. Looking into the “brain” of these “things” the design paradigm of the SoC is emerged. Among the most important challenges facing the SoC design industry today are the cost reduction and the power manage ment. Thus, the industry is consistently looking for new, effective cost and power aware design solutions to apply at the end-products. Such solutions are the dynamic- voltage and frequency scaling, and the partition of the SoC into multiple voltage islan ds, which greatly affect the test process and test cost. This research focuses in the development of an efficient, integrated and computational-friendly methodology able to minimize the test cost of moderate, large and very rge multi core, DVFS based SoC s with voltage islands while power constraints are met.
|Institution and School/Department of submitter:||Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Η/Υ & Πληροφορικής|
|Subject classification:||System-on-chip design and technologies|
|Appears in Collections:||Διδακτορικές Διατριβές|
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|Δ.Δ. ΒΑΡΤΖΙΩΤΗΣ ΦΩΤΙΟΣ 2016.pdf||14.49 MB||Adobe PDF||View/Open|
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