Please use this identifier to cite or link to this item:
https://olympias.lib.uoi.gr/jspui/handle/123456789/11085| Title: | Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands |
| Institution and School/Department of submitter: | Πανεπιστήμιο Ιωαννίνων. Σχολή Θετικών Επιστημών. Τμήμα Μηχανικών Ηλεκτρονικών Υπολογιστών και Πληροφορικής |
| Keywords: | integer programming,linear programming,low-power electronics,multiprocessing systems,scheduling,system-on-chip,core switches,defect screening,dynamic voltage scaling,fast heuristic methods,integer linear programming,low power consumption,multicore system-on-chip,multivoltage domain testing,power supply voltage levels,state retention,test cost,test schedule optimization,test time,voltage islands,Complexity theory,Job shop scheduling,Multicore processing,Optimization,Schedules,System-on-a-chip,Testing,Core-based testing,SoC test scheduling,multicore systems-on-a-chip (SoCs) |
| URI: | https://olympias.lib.uoi.gr/jspui/handle/123456789/11085 |
| ISSN: | 0278-0070 |
| Appears in Collections: | Άρθρα σε επιστημονικά περιοδικά ( Ανοικτά) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| kavousianos-2012-Test Schedule Optimization for Multicore SoCs Handling Dynamic Voltage Scaling and Multiple Voltage Islands.pdf | 3.49 MB | Adobe PDF | View/Open Request a copy |
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